SGI Intros Supercomputer With Intel Nehalem EX
The SGI Altix UV high-performance computing system reaches 18.6 teraflop per second.
By Antone Gonsalves
InformationWeek
November 17, 2009 02:43 PM
SGI HPC System With Intel (NSDQ: INTC) Nehalem EXSGI has introduced a high-performance computing system that can leverage Intel's eight-core Xeon server processor, scheduled to ship early next year.
The SGI Altix UV, unveiled Monday at the SC09 supercomputer conference in Portland, Ore., is targeted at large-scale databases and data analytic environments. The system can combine Intel's highest core chip, codenamed Nehalem EX, with SGI's NUMAlink 5 interconnect to deliver its highest performance of 18.6 teraflop per second. A teraflop is a trillion calculations.
Read Full Article Here:
http://www.informationweek.com/news/hardware/supercomputers/showArticle.jhtml?articleID=221800395&cid=RSSfeed_IWK_ALL
Friday, November 20, 2009
Sunday, November 15, 2009
Intelligent and Expandable High-End Intel® Server Platform, Codenamed Nehalem-EX
As the world’s most widely deployed server, IT has grown to rely on Intel® Xeon® processors for their energy-efficient performance, reliability, and virtualization capabilities built into the hardware. And at this year’s Intel Developer Forum (IDF) in San Francisco, Intel Senior Fellow Stephen Pawlowski took the stage to discuss the next-generation expandable segment server processor, codenamed Nehalem-EX (PDF 205KB). In production in the second half of 2009, its performance increase will be dramatic, posting the highest-ever jump from a previous generation processor1. Nehalem-EX will feature up to eight cores inside a single chip supporting 16 threads and 24 MB of cache. For server consolidation,virtualization, cloud computing, data demanding applications, and other technical computing environments, Nehalem-EX greatly improves scalable performance, memory bandwidth and capacity, flexibility, and provides advanced reliability, availability, and serviceability (RAS) features.
Download the Full PDF Here:
http://ipip.intel.com/go/wp-content/uploads/2009/11/IDF-Tech-Briefing_Nehalem-EX.PDF
Download the Full PDF Here:
http://ipip.intel.com/go/wp-content/uploads/2009/11/IDF-Tech-Briefing_Nehalem-EX.PDF
Friday, November 6, 2009
BMW using Nehalem-EX to save money and boost performance!
From ITPRO.CO.UK:
BMW is also set to switch 1,000 servers to the yet to be released Nehalem EX. For the refresh of two- and four-socket Xeon platform servers, the firm compared EX servers to other suppliers.
“From that, what we got is a smaller energy footprint of four socket with Nehalem than with the existing platform,” he said.
He added the EX lets BMW double its virtualisation ratio, from 10 to 15 virtual machines per server to 20 to 30.
“We think we will order bigger servers in future years as virtualisation is key for our data centre as we have the same power problems,” as faced by many, he said, adding that virtualiation and other efficiencies with Nehalem EX cuts consumption by a third – saving 100,000 euros a year on power use alone.
http://www.itpro.co.uk/617215/bmw-saves-with-nehalem-ep-and-ex
BMW is also set to switch 1,000 servers to the yet to be released Nehalem EX. For the refresh of two- and four-socket Xeon platform servers, the firm compared EX servers to other suppliers.
“From that, what we got is a smaller energy footprint of four socket with Nehalem than with the existing platform,” he said.
He added the EX lets BMW double its virtualisation ratio, from 10 to 15 virtual machines per server to 20 to 30.
“We think we will order bigger servers in future years as virtualisation is key for our data centre as we have the same power problems,” as faced by many, he said, adding that virtualiation and other efficiencies with Nehalem EX cuts consumption by a third – saving 100,000 euros a year on power use alone.
http://www.itpro.co.uk/617215/bmw-saves-with-nehalem-ep-and-ex
Thursday, November 5, 2009
Could IBM be building "glueless" eight-socket systems?
Long time chip industry observer, Eachus, speculates on The Motley Fool:
Hmm. Even in the Intel presentation you linked, slide 15 talks about IBM's 5th generation X series chipset. I do expect IBM to sell standard 4xNehalem-EX boxes, but I think they will use their own chipset in larger systems. Could IBM just be designing an I/O chip of their own, and be building "glueless" eight-socket systems? Possible, but IBM has a lot of institutional knowledge about building multiCPU systems with various CPU ISAs. I'm fairly sure that they would take one look at Beckton and conclude that their existing technology could support two Beckton chips with a little work to convert to what is now called Quickpath. We are talking a few man-years to add Quickpath to their current X-4 chip, vs. hundreds of man years for a complete redesign. Which would you choose? ;-)
http://boards.fool.com/Message.asp?mid=28077140&sort=postdate
Hmm. Even in the Intel presentation you linked, slide 15 talks about IBM's 5th generation X series chipset. I do expect IBM to sell standard 4xNehalem-EX boxes, but I think they will use their own chipset in larger systems. Could IBM just be designing an I/O chip of their own, and be building "glueless" eight-socket systems? Possible, but IBM has a lot of institutional knowledge about building multiCPU systems with various CPU ISAs. I'm fairly sure that they would take one look at Beckton and conclude that their existing technology could support two Beckton chips with a little work to convert to what is now called Quickpath. We are talking a few man-years to add Quickpath to their current X-4 chip, vs. hundreds of man years for a complete redesign. Which would you choose? ;-)
http://boards.fool.com/Message.asp?mid=28077140&sort=postdate
Wednesday, November 4, 2009
Intel Previews Intel Xeon® 'Nehalem-EX' Processor
This new platform from Intel is going to enable so many possibilities!!!
8x8 servers? Wow!
http://www.intel.com/pressroom/archive/releases/20090526comp.htm
8x8 servers? Wow!
http://www.intel.com/pressroom/archive/releases/20090526comp.htm
Intel set to release 8-Socket Glueless platform in early 2010
The demos they were interested were the Nehalem 4-socket demos. They wanted to see this 8-core and 2.3 billion transistors platform and the applications that leverage this 32-core machine. This is an amazing new Intel platform targeted to be released in early 2010. OEM can design 2-socket to 8 socket Nahelem-EX platform gluelessly, and higher configuration with their own node controllers. Currently, we are expecting 15 8-socket and above configuration systems from 8 OEMs to come to the market at launch.
From the Server Room Blog:
http://communities.intel.com/community/openportit/server/blog/authors/hfcheng
From the Server Room Blog:
http://communities.intel.com/community/openportit/server/blog/authors/hfcheng
Tuesday, November 3, 2009
AMD Horus
From Wikipedia:
The Horus system, designed by Newisys for AMD, was created to enable AMD Opteron machines to extend beyond the current limit of 8-way (CPU sockets) architectures. The Opteron CPUs feature a cache-coherent HyperTransport (ccHT) bus to permit glueless, multiprocessor interconnect between physical CPU packages but as there is a maximum of three ccHT interfaces per chip, the systems are limited to a maximum of 8 sockets. The HyperTransport bus is also distance restricted and does not permit off-system interconnect.
The Horus system overcomes these limitations by creating a pseudo-Opteron, the Horus chip, which connects to four real Opterons via the HyperTransport bus. As far as the Opterons are concerned they are in a five-way system and this is the basic Horus node (as called 'quad'). The Horus chip then provides an additional off-board interface (based around the Infiniband standards) which can link to additional Horus nodes (up to 8). The chip handles the necessary translation between local and off-board ccHT communications. By putting the CPUs around the Horus chip with 12-bit lanes running at 3125 MHz with InfiniBand technology (8b/10b encoding), this system has an effective internal speed of 30 Gbit/s.
With 8 'quads' connected together, each with the maximum of four Opteron sockets per node, the Horus system allows a total of 32 CPU sockets in a single machine. Dual and future quad-core chips will also be supported, allowing a single system to scale to over a hundred processing cores.
http://en.wikipedia.org/wiki/AMD_Horus
The Horus system, designed by Newisys for AMD, was created to enable AMD Opteron machines to extend beyond the current limit of 8-way (CPU sockets) architectures. The Opteron CPUs feature a cache-coherent HyperTransport (ccHT) bus to permit glueless, multiprocessor interconnect between physical CPU packages but as there is a maximum of three ccHT interfaces per chip, the systems are limited to a maximum of 8 sockets. The HyperTransport bus is also distance restricted and does not permit off-system interconnect.
The Horus system overcomes these limitations by creating a pseudo-Opteron, the Horus chip, which connects to four real Opterons via the HyperTransport bus. As far as the Opterons are concerned they are in a five-way system and this is the basic Horus node (as called 'quad'). The Horus chip then provides an additional off-board interface (based around the Infiniband standards) which can link to additional Horus nodes (up to 8). The chip handles the necessary translation between local and off-board ccHT communications. By putting the CPUs around the Horus chip with 12-bit lanes running at 3125 MHz with InfiniBand technology (8b/10b encoding), this system has an effective internal speed of 30 Gbit/s.
With 8 'quads' connected together, each with the maximum of four Opteron sockets per node, the Horus system allows a total of 32 CPU sockets in a single machine. Dual and future quad-core chips will also be supported, allowing a single system to scale to over a hundred processing cores.
http://en.wikipedia.org/wiki/AMD_Horus
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